1. Field of the Invention
The present invention relates to a high speed boosting circuit and, more specifically, it relates to a high speed boosting circuit employed in a MOS type integrated circuit and the like.
2. Description of the Prior Art
FIG. 1 is a schematic diagram showing one example of a conventional high speed boosting circuit. Referring to the figure, the circuit comprises a first power supply V.sub.SS (which is selected to be the ground voltage, for example), a second power supply V.sub.CC (which is selected to be the voltage higher than the voltage of the first power supply V.sub.SS), a third power supply V.sub.GG (which is selected to be the voltage higher than the second power supply V.sub.CC), a bootstrap type inverter 100 (hereinafter referred to as a bootstrap circuit) and a driving circuit 200, wherein a signal .phi. having the voltage of approximately the same level as the third power supply V.sub.GG is outputted at high speed to the output signal line L.sub.OUT of the driving circuit 200 in response to the input of an input signal .phi. to the input signal line L.sub.IN of the bootstrap circuit 100. The capacitance C3 is a load capacitance of the output signal line L.sub.OUT.
The operation of the above described circuit will be described in the following. FIG. 4 is a diagram of waveforms illustrating the operation of one embodiment of the present invention which will be described later. However, since the waveforms of the input signal .phi., the precharge signal P and the node A are the same in the circuit of FIG. 1 and, in addition, the waveform of the output signal .phi. in the circuit of FIG. 1 is denoted by a dotted line, the operation of the above described conventional circuit will be described with reference to FIG. 4.
Before the input signal .phi. is inputted to the input signal line L.sub.IN, that is, when the gate voltage of the transistor 3 is at the "H" level, all of the transistors 1 to 3 are turned on and the node A is maintained at the voltage of approximately the same level as that of the first power supply V.sub.SS. When an input signal .phi. of "L" level is applied to the input signal line L.sub.IN in this state, the transistor 3 turns off and the voltage at the node A rises rapidly. Consequently, the gate voltage of the transistor 2 is boosted higher than the voltage of the second power supply V.sub.CC by the boost function of the capacitor C1, strongly turning the transistor 2 on. Therefore, the impedance between the drain and source of the transistor 2 becomes extremely low, and the voltage at the node A is boosted to approximately the same level as the voltage of the second power supply V.sub.CC.
When the node A reaches approximately the same level as the second power supply V.sub.CC, a transistor 8 in the driving circuit 200 turns on to charge the node B. Correspondingly, a transistor 9 turns on and the voltage of the output signal .phi. gradually increases. When the output signal .phi. rises, a transistor 5 turns on, so that the node C discharges and a transistor 6 turns off. Consequently, the voltage at the node D begins to rise and the voltage at the node B is boosted higher than the voltage level of the second power supply V.sub.CC through the capacitor C2. Therefore, the transistor 9 strongly turns on and the voltage level of the third power supply V.sub.GG appears on the output signal .phi..
In the conventional circuit such as described above, the voltage of the second power supply V.sub.CC is boosted on the semiconductor chip to obtain a voltage V.sub.GG which is higher than the second power supply V.sub.CC and by employing this voltage V.sub.GG, an output signal .phi. having the voltage level higher than that of the second power supply V.sub.CC is generated. Therefore, the third power supply V.sub.GG is provided on the semiconductor chip as an internal power supply. A power supply such as shown in FIG. 2 is conventionally used as the internal power supply. The internal power supply shown in FIG. 2 comprises three inverters 12a to 12c, two transistors 13 and 14, and two capacitors C4 and C5. However, since the impedance of the above described internal power supply is extremely high in general, it has small ability of current supply. Therefore, the "H" level voltage of the output signal .phi. may possibly become low dependent on the magnitude of the load capacitance C3 of the output signal line L.sub.OUT and on the frequency of the input signal .phi..
The following articles disclose other prior arts.
(1) IEEE Journal of Solid-State Circuits Vol. SC-15 No. 5 October 1980 "A 100 ns 5 V Only 64K .times.1 MOS Dynamic RAM" pp. 839.about.846 (especially in FIG. 11(a), High Voltage Generator Circuit)
(2) IEEE Journal of Solid-State Circuits Vol. SC-16 No. 5 October 1981 "FULLY BOOSTED 64K DYNAMIC RAM WITH AUTOMATIC AND SELF-REFRESH" pp. 492-498 (especially in FIG. 2, Boosted Word Line Clock Generator)
The circuit shown in the above article (1) and the circuit shown in the above article (2) have the same defect as the conventional circuit of FIG. 1 or the defect of slow boosting speed.